1. Field of the Invention
The present invention relates to a semiconductor apparatus. More particularly, the present invention relates to a semiconductor apparatus for improving an operational performance of CMOS (Complementary Metal Oxide Semiconductor) circuits, and a method of manufacturing the same.
2. Description of the Related Art
FIG. 1 shows a typical conventional CMOS circuit. The CMOS circuit includes CMOS inverters 1 and 2. The CMOS inverter 1 includes a PMOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistor) 3 and an NMOSFET (N-channel MOSFET) 4. A source of the PMOSFET 1 is connected to power supply terminal VDD and a source of the NMOSFET 4 is connected to a ground terminal GND. The PMOSFET 3 and the NMOSFET 4 are connected on their drains and the drains are used as an output terminal OUT1 of the CMOS inverter 1. Gates of the PMOSFET 3 and the NMOSFET are connected to each other and used as an input terminal IN1. The CMOS inverter 2 includes a PMOSFET 5 and an NMOSFET 6 and has the same configuration as the CMOS inverter 1. The output terminal OUT1 of the CMOS inverters 1 is connected to an input terminal IN2 of the CMOS inverter 2.
The CMOS circuit shown in FIG. 1 is used for a buffer. When a rectangular signal is inputted to the input terminal IN1 of the CMOSFET 1, the CMOS inverter 1 inverts the rectangular signal to output to the CMOS inverter 2. The CMOS inverter 2 inverts the inverted rectangular signal to output from the output terminal OUT2. Then, a rectangular signal is outputted from the output terminal OUT2, representing the same logical value as the rectangular signal inputted to the input terminal IN1.
The operation speed of the CMOS circuit depends on operating currents of the MOSFETs. As for the CMOS inverter 1, the PMOSFET 3 is turned off and the NMOSFET 4 is turned on in response to the pull-up of the input signal inputted to the input terminal IN1. The NMOSFET 4 generates the operating current from the output terminal OUT2 to the grounded terminal to pull down the output terminal OUT1. When the input signal is pulled down, the PMOSFET 3 is turned on and the NMOSFET 4 is turned off. The PMOSFET 3 generates the operating current from the power supply terminal Vcc to the output terminal OUT1 to pull up the output terminal OUT1. As the operating currents of the respective MOSFETs are larger, the operation speed of the CMOS circuit is improved.
The increase of the operating current is achieved by reducing the impurity concentration of channel regions of the MOSFETS. The operating current in the MOSFETs depends on the impurity concentration of channel regions of the MOSFETs. A decrease in the impurity concentration of the channel region results in an increase in the operating current, because the decreased impurity concentration reduces the scattering of the carriers in the channel region and thereby increases the operation speed of the carriers.
In the conventional CMOS circuit, however, the impurity concentration of the channel regions must be fixed to obtain a predetermined threshold voltage Vth, which is defined by amplitude of signal in the CMOS circuit. The impurity concentration is a main factor to determine the threshold voltage Vth of MOSFETs. The decrease of the impurity concentration of the channel region of the NMOSFET for improving the operating current is accompanied by a decrease in positive threshold voltage Vth of the NMOSFET, that is, the threshold voltage Vth of the NMOSFET shifts toward a negative voltage. Also, the decrease of the impurity concentration of the channel region of the PMOSFET for improving the operating current is accompanied by decrease a negative voltage Vth in the PMOSFET, that is, the negative threshold voltage Vth of the PMOSFET shifts toward a positive voltage. Here and hereinafter, an increase of the threshold voltage Vth implies an increase in an absolute value of the threshold voltage Vth. Also, a decrease of the threshold voltage Vth implies a decrease in an absolute value of the threshold voltage Vth. Thus, the channel impurity concentration is not defined so as to improve the operating current.
Mogami discloses a CMOS technology in Japanese Laid Open Patent Application (JP-A-Heisei 5-267333), which may be related to the present invention. Mogami discloses a method for improving a hot carrier resistance by introducing fluorine ions into the gate insulator.
Also, Miura discloses another CMOS technique in Japanese Laid Open Patent Application (JP-A-Heisei 2000-124455). Miura discloses a method for removing or decreasing the positive fixed charges in the gate insulator by applying ultra violet light to the gate insulator.
The present invention is to provide a technique for improving an operational performance of a CMOS circuit by increasing an operating current of MOSFETs.
In order to achieve an aspect of the present invention, a semiconductor apparatus is composed of a P-channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) an N-channel MISFET. The P-channel MISFET includes a first gate insulator which contains first positive charges therein. The N-channel MISFET includes a second gate insulator which contains second positive charges therein. A first charge density of the first positive charge is larger than a second charge density of the second positive charge.
The first charge density is preferably three to four times as large as the second charge density.
The first and second gate insulators are preferably formed of silicon oxinitride.
The first positive charges are preferably induced by nitrogen ions.
The second positive charges are preferably induced by nitrogen ions.
In order to achieve another aspect of the present invention, a semiconductor apparatus is composed of a P-channel MISFET and an N-channel MISFET. The P-channel MISFET includes a first gate insulator which contains positive charges therein. The N-channel MISFET includes a second gate insulator which contains substantially no charge therein.
For this case, the first and second gate insulators are preferably formed of silicon oxide.
In order to achieve still another aspect of the present invention, a semiconductor apparatus is composed of a P-channel MISFET and an N-channel MISFET. The P-channel MISFET includes a first gate insulator which contains substantially no charge therein. The N-channel MISFET includes a second gate insulator which contains negative charges therein.
The negative charges are preferably induced by fluorine ions.
In order to achieve still another aspect of the present invention, a semiconductor apparatus is composed of a P-channel MISFET and an N-channel MISFET. The P-channel MISFET includes a first gate insulator which contains positive charges therein. The N-channel MISFET includes a second gate insulator which contains negative charges therein.
In order to achieve still another aspect of the present invention, a method for fabricating a semiconductor apparatus is composed of:
providing an N region in a surface portion of a substrate for a P-channel MISFET;
providing a P region in another surface portion of the substrate for an N-channel MISFET;
forming a silicon oxinitride film containing positive charges on the N region and P region, the silicon oxinitride film including:
a first portion located on the N region and,
a second portion located on the P region;
annealing the silicon oxinitride film to adjust a charge density in the silicon oxinitride film such that a first charge density of the first portion is larger than a second charge density of the second portion; and
forming gate electrodes on the silicon oxinitride film after the annealing.
The annealing is preferably executed for substantially one minute at a temperature between 1000 to 1100xc2x0 C.
The first charge density is three to four times as large as the second charge density
In order to achieve still another aspect of the present invention, a method for fabricating a semiconductor apparatus is composed of:
providing an N region in a surface portion of a substrate for a P-channel MISFET;
providing a P region in another surface portion of the substrate for an N-channel MISFET;
forming a first gate insulator of a on the N region;
forming a second gate insulator on the P region; and
introducing positive charges into the first gate insulator while introducing substantially no positive charge into the second gate insulator.
In this case, it is preferable that the method is further composed of forming a gate electrode on the first gate insulator, and the introducing includes:
implanting nitrogen ions into the gate electrode; and
diffusing the nitrogen ions into the first gate insulator by annealing.
In order to achieve still another aspect of the present invention, a method for fabricating a semiconductor apparatus is composed of:
providing an N region in a surface portion of a substrate for a P-channel MISFET;
providing a P region in another surface portion of the substrate for an N-channel MISFET;
forming a first gate insulator on the N region;
forming a second gate insulator on the P region;
forming a first gate electrode on the first gate insulator;
forming a second gate electrode on the second gate insulator; and
introducing negative charges into the second gate insulator while introducing substantially no negative charge into the first gate insulator.
It is preferable that the method is further composed of forming a gate electrode on the second gate insulator, and the introducing includes:
implanting fluorine ions into the gate electrode; and
diffusing the fluorine ions into the second gate insulator by annealing.
In order to achieve still another aspect of the present invention, a method for fabricating a semiconductor apparatus is composed of:
providing an N region in a surface portion of a substrate for a P-channel MISFET;
providing a P region in another surface portion of the substrate for an N-channel MISFET;
forming a first gate insulator on the N region;
forming a second gate insulator on the P region;
forming a first gate electrode on the first gate insulator;
forming a second gate electrode on the second gate insulator;
introducing positive charges into the first gate insulator; and
introducing negative charges into the second gate insulator.